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VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 4 months ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...
INFOCOM
2006
IEEE
15 years 10 months ago
Achieving Repeatability of Asynchronous Events in Wireless Sensor Networks with EnviroLog
— Sensing events from dynamic environments are normally asynchronous and non-repeatable. This lack of repeatability makes it particularly difficult to statistically evaluate the...
Liqian Luo, Tian He, Gang Zhou, Lin Gu, Tarek F. A...
ICPP
1997
IEEE
15 years 8 months ago
Communication in Parallel Applications: Characterization and Sensitivity Analysis
Communication characterization of parallel applications is essential to understand the interplay between architectures and applications in determining the maximum achievable perfo...
Dale Seed, Anand Sivasubramaniam, Chita R. Das
PIMRC
2010
IEEE
15 years 2 months ago
Improving link failure detection and response in IEEE 802.11 wireless ad hoc networks
Wireless multihop ad hoc networks face a multitude of challenging problems including highly dynamic multihop topologies, lossy and noisy communications channels, and sporadic conne...
Alvin C. Valera, Hwee-Pink Tan, Winston Khoon Guan...
IPPS
1998
IEEE
15 years 8 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf