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CODES
2006
IEEE
14 years 2 months ago
A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation
Traditionally, instruction-set simulators (ISS’s) are sequential programs running on individual processors. Besides the advances of simulation techniques, ISS’s have been main...
Wei Qin, Joseph D'Errico, Xinping Zhu
FCCM
2008
IEEE
205views VLSI» more  FCCM 2008»
14 years 3 months ago
Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation
The recent turmoil in global credit markets has demonstrated the need for advanced modelling of credit risk, which can take into account the effects of changing economic condition...
David B. Thomas, Wayne Luk
FPGA
2008
ACM
136views FPGA» more  FPGA 2008»
13 years 10 months ago
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs
Functional full-system simulators are powerful and versatile research tools for accelerating architectural exploration and advanced software development. Their main shortcoming is...
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Bab...
VTC
2008
IEEE
106views Communications» more  VTC 2008»
14 years 2 months ago
Simulation-Based Performance Evaluation of Enhanced Broadcast Schemes for IEEE 802.11-Based Vehicular Networks
—Car-to-car communication (C2CC) enables cars to exchange information that can be used to, e.g., improve the drivers’ safety or comfort. Recently, WLANs based on the IEEE 802.1...
Yvonne Mertens, Matthias Wellens, Petri Mäh&o...
MSS
1999
IEEE
140views Hardware» more  MSS 1999»
14 years 25 days ago
Pursuit of a Scalable High Performance Multi-Petabyte Database
When the BaBar experiment at the Stanford Linear Accelerator Center starts in April 1999, it will generate approximately 200TB/year of data at a rate of 10MB/sec for 10 years. A m...
Andrew Hanushevsky, Marcia Nowark