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» Evaluating kilo-instruction multiprocessors
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APCSAC
2007
IEEE
14 years 1 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
13 years 11 months ago
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip
Abstract-- Multiprocessor designs have become popular in embedded domains for achieving the power and performance requirements. In this paper, we present principles and techniques ...
Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
PDPTA
1996
13 years 8 months ago
Evaluation of Dynamic Data Distributions on NUMA Shared Memory Multiprocessors
Dynamic data distributions offer a number of performance benefits, but require more sophisticated compiler support and incur run-time overhead. We investigate attainable benefits ...
Tarek S. Abdelrahman, Kenneth L. Ma
MAM
2002
151views more  MAM 2002»
13 years 7 months ago
A performance evaluation of cache injection in bus-based shared memory multiprocessors
Bus-based shared memory multiprocessors with private caches and snooping write-invalidate cache coherence protocols are dominant form of small- to medium-scale parallel machines t...
Aleksandar Milenkovic, Veljko M. Milutinovic
CAL
2006
13 years 7 months ago
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to achieve the highest performance for a given power budget. ACCMPs execute serial ...
T. Y. Morad, Uri C. Weiser, A. Kolodnyt, Mateo Val...