417 search results - page 68 / 84 » Evaluating kilo-instruction multiprocessors |
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
RTCSA
2007
IEEE
14 years 1 months ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Achieving high performance for concurrent applications on modern multiprocessors remains challenging. Many programmers avoid locking to improve performance, while others replace l...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ANCS
2006
ACM
14 years 1 months ago
2006
ACM
Load balancing in packet-switched networks is a task of ever-growing importance. Network traffic properties, such as the Zipf-like flow length distribution and bursty transmissio...