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» Evaluating kilo-instruction multiprocessors
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DAC
2010
ACM
13 years 11 months ago
Cost-aware three-dimensional (3D) many-core multiprocessor design
The emerging three-dimensional integrated circuit (3D IC) is beneficial for various applications from both area and performance perspectives. While the general trend in processor...
Jishen Zhao, Xiangyu Dong, Yuan Xie
IPPS
1998
IEEE
13 years 11 months ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...
ICDCS
1996
IEEE
13 years 11 months ago
The Performance Value of Shared Network Caches in Clustered Multiprocessor Workstations
This paper evaluates the bene t of adding a shared cache to the network interface as a means of improving the performance of networked workstations con gured as a distributed shar...
John K. Bennett, Katherine E. Fletcher, William Ev...
TCAD
2008
215views more  TCAD 2008»
13 years 7 months ago
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric
Abstract--This paper proposes an algorithm that provides both dynamic voltage scaling and power shutdown to minimize the total energy consumption of an application executed on an o...
Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho A...
SIGMETRICS
2012
ACM
251views Hardware» more  SIGMETRICS 2012»
11 years 10 months ago
Providing fairness on shared-memory multiprocessors via process scheduling
Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbate...
Di Xu, Chenggang Wu, Pen-Chung Yew, Jianjun Li, Zh...