26 search results - page 2 / 6 » Evaluating the Impact of Fault Recovery on Superscalar Proce... |
ISCA
2002
IEEE
14 years 16 days ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
MICRO
1998
IEEE
13 years 12 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
DSN
2006
IEEE
14 years 1 months ago
2006
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
GLVLSI
2010
IEEE
14 years 21 days ago
2010
IEEE
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Fault tolerance in MPI becomes a main issue in the HPC community. Several approaches are envisioned from user or programmer controlled fault tolerance to fully automatic fault ...