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CODES
2006
IEEE
14 years 1 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ISPASS
2009
IEEE
14 years 2 months ago
Accurately approximating superscalar processor performance from traces
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
Kiyeon Lee, Shayne Evans, Sangyeun Cho
EICS
2009
ACM
14 years 2 months ago
Engineering crowd interaction within smart environments
Smart environments (e.g., airports, hospitals, stadiums, and other physical spaces using ubiquitous computing to empower many mobile people) provide novel challenges for usability...
Michael D. Harrison, Mieke Massink, Diego Latella
HIPS
1997
IEEE
13 years 11 months ago
Complexity and Performance in Parallel Programming Languages
Several parallel programming languages, libraries and environments have been developed to ease the task of writing programs for multiprocessors. Proponents of each approach often ...
Steven P. Vanderwiel, Daphna Nathanson, David J. L...
IIE
2007
154views more  IIE 2007»
13 years 7 months ago
Computer Aided Modelling Exercises
This paper describes a didactical Computer Aided Software Engineering (CASE)-tool that was developed for use within the context of a course in object-oriented domain modelling. In...
Monique Snoeck, Raf Haesen, Herman Buelens, Manu D...