366 search results - page 12 / 74 » Evaluating the Performance of Skeleton-Based High Level Para... |
ISCAS
2005
IEEE
14 years 2 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
PPOPP
2006
ACM
14 years 2 months ago
2006
ACM
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
In recent years, we have witnessed a growing interest in high performance computing (HPC) using a cluster of workstations. However, many challenges remain to be resolved before th...
PADS
2006
ACM
14 years 2 months ago
2006
ACM
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
HPCA
2008
IEEE
14 years 8 months ago
2008
IEEE
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...