207 search results - page 12 / 42 » Evaluating the Performance of Software Cache Coherence |
HPCA
2012
IEEE
12 years 3 months ago
2012
IEEE
Large-scale CMPs with hundreds of cores require a directory-based protocol to maintain cache coherence. However, previously proposed coherence directories are hard to scale beyond...
MSE
2002
IEEE
14 years 12 days ago
2002
IEEE
This paper presents the study of running several core multimedia applications on a simultaneous multithreading (SMT) architecture and derives design principles for multimedia soft...
HIPEAC
2010
Springer
13 years 5 months ago
2010
Springer
We propose a new design for an energy-efficient hardware transactional memory (HTM) system for power-aware embedded devices. Prior hardware transactional memory designs proposed a ...
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...