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ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 3 months ago
Late-binding: enabling unordered load-store queues
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
Simha Sethumadhavan, Franziska Roesner, Joel S. Em...
ARCS
2006
Springer
14 years 25 days ago
Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...
Chen-Yong Cher, Il Park, T. N. Vijaykumar
CIBCB
2008
IEEE
14 years 3 months ago
Discovering novel cancer therapies: A computational modeling and search approach
— Solid tumors must recruit new blood vessels for growth and maintenance. Discovering drugs that block this tumor-induced development of new blood vessels (angiogenesis) is an im...
Arthur W. Mahoney, Brian G. Smith, Nicholas S. Fla...
ICFP
2009
ACM
14 years 9 months ago
Effective interactive proofs for higher-order imperative programs
We present a new approach for constructing and verifying higherorder, imperative programs using the Coq proof assistant. We build on the past work on the Ynot system, which is bas...
Adam J. Chlipala, J. Gregory Malecha, Greg Morrise...
CODES
2006
IEEE
14 years 3 months ago
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
Roshan G. Ragel, Sri Parameswaran