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CODES
2008
IEEE
13 years 9 months ago
A performance-oriented hardware/software partitioning for datapath applications
This article proposes a hardware/software partitioning method targeted to performance-constrained systems for datapath applications. Exploiting a platform based design, a Timed Pe...
Laura Frigerio, Fabio Salice
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 8 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
CONEXT
2007
ACM
13 years 11 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
ASPLOS
2009
ACM
14 years 2 months ago
Architectural implications of nanoscale integrated sensing and computing
This paper explores the architectural implications of integrating computation and molecular probes to form nanoscale sensor processors (nSP). We show how nSPs may enable new compu...
Constantin Pistol, Christopher Dwyer, Alvin R. Leb...
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
13 years 5 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar