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CONEXT
2007
ACM
13 years 10 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
PLDI
2000
ACM
13 years 11 months ago
Dynamo: a transparent dynamic optimization system
We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stre...
Vasanth Bala, Evelyn Duesterwald, Sanjeev Banerjia
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
13 years 11 months ago
Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
Anoop Iyer, Diana Marculescu
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
VEE
2012
ACM
252views Virtualization» more  VEE 2012»
12 years 2 months ago
libdft: practical dynamic data flow tracking for commodity systems
Dynamic data flow tracking (DFT) deals with tagging and tracking data of interest as they propagate during program execution. DFT has been repeatedly implemented by a variety of ...
Vasileios P. Kemerlis, Georgios Portokalidis, Kang...