54 search results - page 3 / 11 » Evaluation of CORDIC Algorithms for FPGA Design |
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This paper presents an equation-based resource utilization model for automatically generated discrete Fourier transform (DFT) soft core IPs. The parameterized DFT IP generator all...
RECONFIG
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—The main challenge when implementing cryptographic algorithms in hardware is to protect them against attacks that target directly the device. Two strategies are customar...
FPGA
2004
ACM
14 years 23 days ago
2004
ACM
As FPGA densities increase, partitioning-based FPGA placement approaches are becoming increasingly important as they can be used to provide high-quality and computationally scalab...
AHS
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper describes a new FPGA implementation of a system for evolutionary image filter design. Three parallel search algorithms are compared. An optimal mutation rate and the q...