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» Evaluation of CORDIC Algorithms for FPGA Design
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JCP
2008
119views more  JCP 2008»
13 years 7 months ago
Performance Comparisons, Design, and Implementation of RC5 Symmetric Encryption Core using Reconfigurable Hardware
With the wireless communications coming to homes and offices, the need to have secure data transmission is of utmost importance. Today, it is important that information is sent con...
Omar S. Elkeelany, Adegoke Olabisi
OSN
2011
12 years 10 months ago
A parallel iterative scheduler for asynchronous Optical Packet Switching networks
—This paper presents PI-OPS (Parallel-Iterative Optical Packet Scheduler) a parallel-iterative scheduler for asynchronous Optical Packet Switching nodes with optical buffering. O...
Pablo Pavón-Mariño, M. Victoria Buen...
IPPS
2007
IEEE
14 years 1 months ago
Reconfigurable Architecture for Biological Sequence Comparison in Reduced Memory Space
DNA sequence alignment is a very important problem in bioinformatics. The algorithm proposed by Smith-Waterman (SW) is an exact method that obtains optimal local alignments in qua...
Azzedine Boukerche, Jan Mendonca Correa, Alba Cris...
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
14 years 1 months ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...
SIGCOMM
2010
ACM
13 years 7 months ago
SwitchBlade: a platform for rapid deployment of network protocols on programmable hardware
We present SwitchBlade, a platform for rapidly deploying custom protocols on programmable hardware. SwitchBlade uses a pipeline-based design that allows individual hardware module...
Muhammad Bilal Anwer, Murtaza Motiwala, Muhammad M...