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» Evaluation of Space Allocation Circuits
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CODES
2006
IEEE
14 years 2 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
ASPLOS
2010
ACM
14 years 24 days ago
An asymmetric distributed shared memory model for heterogeneous parallel systems
Heterogeneous computing combines general purpose CPUs with accelerators to efficiently execute both sequential control-intensive and data-parallel phases of applications. Existin...
Isaac Gelado, Javier Cabezas, Nacho Navarro, John ...
ICOIN
2001
Springer
14 years 12 days ago
A Proxy Caching Scheme for Continuous Media Streams on the Internet
The Internet has enabled the dissemination and access of vast amounts of information to be easy. But dramatic increases of the number of users of Internet cause server overload, n...
Eun-Ji Lim, Seong-Ho Park, Hyeon-Ok Hong, Ki-Dong ...
ASPLOS
2008
ACM
13 years 10 months ago
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
Michal Wegiel, Chandra Krintz
ICS
2004
Tsinghua U.
14 years 1 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer