87 search results - page 13 / 18 » Evaluation of a Multithreaded Architecture for Cellular Comp... |
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper we explore the impact of the block shape on blocked and vectorized versions of the Sparse Matrix-Vector Multiplication (SpMV) kernel and build upon previous work by ...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
ICS
2004
Tsinghua U.
14 years 28 days ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
MOBICOM
2010
ACM
13 years 7 months ago
2010
ACM
Femtocell technology has been drawing considerable attention as a cost-effective means of improving cellular coverage and capacity. However, under co-channel deployment, femtocell...