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AHS
2007
IEEE
215views Hardware» more  AHS 2007»
13 years 7 months ago
Online Evolution for a High-Speed Image Recognition System Implemented On a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga
ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
14 years 2 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
PPOPP
2003
ACM
14 years 22 days ago
User-controllable coherence for high performance shared memory multiprocessors
In programming high performance applications, shared address-space platforms are preferable for fine-grained computation, while distributed address-space platforms are more suita...
Collin McCurdy, Charles N. Fischer
HIPC
2009
Springer
13 years 5 months ago
Comparing the performance of clusters, Hadoop, and Active Disks on microarray correlation computations
Abstract--Microarray-based comparative genomic hybridization (aCGH) offers an increasingly fine-grained method for detecting copy number variations in DNA. These copy number variat...
Jeffrey A. Delmerico, Nathanial A. Byrnes, Andrew ...
CCGRID
2005
IEEE
14 years 1 months ago
A batch scheduler with high level components
In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emp...
Nicolas Capit, Georges Da Costa, Yiannis Georgiou,...