Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...
High-speed wireless backbones have the potential to replace or complement wired connections. This paper provides a comprehensive network and transport layer performance evaluation...
Roger Karrer, Istvan Matyasovszki, Alessio Botta, ...
This paper presents an architecture that makes it possible to construct dynamic systems capable of growing in dimension and adapting its knowledge to environmental changes. An arch...
We propose a comprehensive theoretical framework to evaluate reliability and energy consumption of distributed source coding (DSC) in wireless sensor networks (WSNs) applications. ...
Carlo Fischione, Stefano Tennina, Fortunato Santuc...