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ICS
2001
Tsinghua U.
13 years 11 months ago
Integrating superscalar processor components to implement register caching
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a l...
Matt Postiff, David Greene, Steven E. Raasch, Trev...
HICSS
2000
IEEE
147views Biometrics» more  HICSS 2000»
13 years 11 months ago
ViCA - A WWW based Tool for Visualizing Project Status
Easy-to-access and up-to-date project status feedback is an important aspect of effective project management. When project data is collected, a common problem is how to present th...
Pekka Kilponen, Jari Vanhanen
CSFW
1999
IEEE
13 years 11 months ago
Athena: A New Efficient Automatic Checker for Security Protocol Analysis
We propose an efficient automatic checking algorithm, Athena, for analyzing security protocols. Athena incorporates a logic that can express security properties including authenti...
Dawn Xiaodong Song
VISUALIZATION
1999
IEEE
13 years 11 months ago
Multi-Projector Displays Using Camera-Based Registration
Conventional projector-based display systems are typically designed around precise and regular configurations of projectors and display surfaces. While this results in rendering s...
Ramesh Raskar, Michael S. Brown, Ruigang Yang, Wei...
MICRO
1998
IEEE
89views Hardware» more  MICRO 1998»
13 years 11 months ago
Load Latency Tolerance in Dynamically Scheduled Processors
This paper provides quantitative measurements of load latency tolerance in a dynamically scheduled processor. To determine the latency tolerance of each memory load operation, our...
Srikanth T. Srinivasan, Alvin R. Lebeck