13631 search results - page 99 / 2727 » Event-Based Performance Analysis |
ICIP
2000
IEEE
14 years 12 months ago
2000
IEEE
VIRAM (Vector Intelligent Random Access Memory) is a vector architecture processor with embedded memory, designed for portable multimedia processing devices. Its vector processing...
DAC
2000
ACM
14 years 11 months ago
2000
ACM
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
DAC
2001
ACM
14 years 11 months ago
2001
ACM
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
ICCAD
2006
IEEE
14 years 7 months ago
2006
IEEE
Early evaluation allows to execute operations when enough information at the inputs has been received to determine the value at the outputs. Systems that can tolerate variable-lat...
IPPS
2009
IEEE
14 years 5 months ago
2009
IEEE
Although processors become massively multicore and therefore new programming models mix message passing and multi-threading, the effects of threads on communication libraries rema...