Sciweavers

59 search results - page 5 / 12
» Evolution-Based Scheduling of Fault-Tolerant Programs on Mul...
Sort
View
ASPLOS
2009
ACM
14 years 8 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
APPT
2009
Springer
14 years 1 months ago
A Fast Scheme to Investigate Thermal-Aware Scheduling Policy for Multicore Processors
Abstract. With more cores integrated into one single chip, the overall power consumption from the multiple concurrent running programs increases dramatically in a CMP processor whi...
Liqiang He, Cha Narisu
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
14 years 19 days ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
ASPLOS
2000
ACM
13 years 11 months ago
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
Simultaneous Multithreading machines fetch and execute instructions from multiple instruction streams to increase system utilization and speedup the execution of jobs. When there ...
Allan Snavely, Dean M. Tullsen
CASES
2001
ACM
13 years 11 months ago
Combined partitioning and data padding for scheduling multiple loop nests
With the widening performance gap between processors and main memory, efficient memory accessing behavior is necessary for good program performance. Loop partition is an effective...
Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu