718 search results - page 126 / 144 » Evolvable Hardware for Space Applications |
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
CA
2002
IEEE
14 years 26 days ago
2002
IEEE
A facial analysis-synthesis framework based on a concise set of local, independently actuated, Coarticulation Regions (CR) is presented for the control of 2D animated characters. ...
ICCD
2000
IEEE
14 years 9 days ago
2000
IEEE
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
LCTRTS
1999
Springer
14 years 4 days ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
PPOPP
1993
ACM
13 years 12 months ago
1993
ACM
This paper discusses some of the issues involved in implementing a shared-address space programming model on large-scale, distributed-memory multiprocessors. While such a programm...