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EH
1999
IEEE
122views Hardware» more  EH 1999»
14 years 8 days ago
The MorphoSys Dynamically Reconfigurable System-on-Chip
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Ba...
ICES
2010
Springer
148views Hardware» more  ICES 2010»
13 years 6 months ago
HyperNEAT for Locomotion Control in Modular Robots
Abstract. In an application where autonomous robots can amalgamate spontaneously into arbitrary organisms, the individual robots cannot know a priori at which location in an organi...
Evert Haasdijk, Andrei A. Rusu, A. E. Eiben
GECCO
2006
Springer
141views Optimization» more  GECCO 2006»
13 years 11 months ago
Coevolution of neural networks using a layered pareto archive
The Layered Pareto Coevolution Archive (LAPCA) was recently proposed as an effective Coevolutionary Memory (CM) which, under certain assumptions, approximates monotonic progress i...
German A. Monroy, Kenneth O. Stanley, Risto Miikku...
CMG
2003
13 years 9 months ago
{Performance Modeling and Evaluation of Large-Scale J2EE Applications
The queueing Petri net (QPN) paradigm provides a number of benefits over conventional modeling paradigms such as queueing networks and generalized stochastic Petri nets. Using qu...
Samuel Kounev, Alejandro P. Buchmann
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
14 years 1 months ago
Studying Storage-Recomputation Tradeoffs in Memory-Constrained Embedded Processing
Fueled by an unprecedented desire for convenience and self-service, consumers are embracing embedded technology solutions that enhance their mobile lifestyles. Consequently, we wi...
Mahmut T. Kandemir, Feihui Li, Guilin Chen, Guangy...