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EVOW
2008
Springer
13 years 8 months ago
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures
Abstract. In this paper we propose three small instances of a reconfigurable circuit and analyze their properties using the brute force method and evolutionary algorithm. Although ...
Lukás Sekanina, Petr Mikusek
CEC
2008
IEEE
14 years 1 months ago
Fitness functions for the unconstrained evolution of digital circuits
— This work is part of a project that aims to develop and operate integrated evolvable hardware systems using unconstrained evolution. Experiments are carried out on an evolvable...
Tüze Kuyucu, Martin Trefzer, Andrew J. Greens...
DSD
2007
IEEE
83views Hardware» more  DSD 2007»
14 years 1 months ago
Hierarchical Identification of Untestable Faults in Sequential Circuits
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kru...
ICES
2001
Springer
91views Hardware» more  ICES 2001»
13 years 11 months ago
Untidy Evolution: Evolving Messy Gates for Fault Tolerance
Abstract. The exploitation of the physical characteristics has already been demonstrated in the intrinsic evolution of electronic circuits. This paper is an initial attempt at crea...
Julian F. Miller, Morten Hartmann
EH
1999
IEEE
169views Hardware» more  EH 1999»
13 years 11 months ago
GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices
GeneticFPGA is a Java-based tool for evolving digital circuits on Xilinx XC4000EXTM and XC4000XLTM devices. Unlike other FPGA architectures popular with Evolutionary Hardware rese...
Delon Levi, Steve Guccione