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IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 2 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
CCS
2001
ACM
14 years 1 months ago
Interoperable strategies in automated trust negotiation
Automated trust negotiation is an approach to establishing trust between strangers through the exchange of digital credentials and the use of access control policies that specify ...
Ting Yu, Marianne Winslett, Kent E. Seamons
TC
2008
13 years 8 months ago
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
Assaf Shacham, Keren Bergman, Luca P. Carloni
PODC
2004
ACM
14 years 1 months ago
Gradient clock synchronization
We introduce the distributed gradient clock synchronization problem. As in traditional distributed clock synchronization, we consider a network of nodes equipped with hardware clo...
Rui Fan, Nancy A. Lynch
IMC
2009
ACM
14 years 3 months ago
Understanding slow BGP routing table transfers
Researchers and network operators often say that BGP table transfers are slow. Despite this common knowledge, the reasons for slow BGP transfers are not well understood. This pape...
Zied Ben-Houidi, Mickael Meulle, Renata Teixeira