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IEEEPACT
1999
IEEE
14 years 2 months ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
EMSOFT
2003
Springer
14 years 3 months ago
Schedule-Carrying Code
We introduce the paradigm of schedule-carrying code (SCC). A hard real-time program can be executed on a given platform only if there exists a feasible schedule for the real-time t...
Thomas A. Henzinger, Christoph M. Kirsch, Slobodan...
APCSAC
2001
IEEE
14 years 1 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
LCTRTS
1999
Springer
14 years 2 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...