453 search results - page 11 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
CF
2005
ACM
13 years 9 months ago
2005
ACM
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
EMSOFT
2010
Springer
13 years 5 months ago
2010
Springer
We propose a technique to automatically synthesize programs and schedules for hard real-time distributed (embedded) systems from synchronous data-flow models. Our technique connec...
IJPP
2000
13 years 7 months ago
2000
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...