453 search results - page 13 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
MEMOCODE
2008
IEEE
14 years 2 months ago
2008
IEEE
—Caches are commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. The cache performance strongly influences a system’...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
RTAS
2010
IEEE
13 years 6 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...
HOTOS
2009
IEEE
13 years 11 months ago
2009
IEEE
High performance on multicore processors requires that schedulers be reinvented. Traditional schedulers focus on keeping execution units busy by assigning each core a thread to ru...
PC
2012
12 years 3 months ago
2012
— The frenetic development of the current architectures places a strain on the current state-of-the-art programming environments. Harnessing the full potential of such architectu...