453 search results - page 21 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPDC
2008
IEEE
14 years 2 months ago
2008
IEEE
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream progra...
JSA
2008
13 years 7 months ago
2008
Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However...
RTSS
1999
IEEE
13 years 12 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...