453 search results - page 33 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
EUROPAR
2009
Springer
13 years 11 months ago
2009
Springer
Abstract. In the field of HPC, the current hardware trend is to design multiprocessor architectures that feature heterogeneous technologies such as specialized coprocessors (e.g., ...
HPCC
2007
Springer
14 years 1 months ago
2007
Springer
Computing ”in-place and in-order”FFT poses a very difficult problem on hierarchical memory architectures where data movement can seriously degrade the performance. In this pape...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
SIGARCH
2008
13 years 7 months ago
2008
As multicore architectures gain widespread use, it becomes increasingly important to be able to harness their additional processing power to achieve higher performance. However, e...
ISPAN
1997
IEEE
13 years 12 months ago
1997
IEEE
The thesis of this research is that the task of exposing the parallelism in a given application should be left to the algorithm designer, who has intimate knowledge of the applica...