453 search results - page 35 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
EUROPAR
2003
Springer
14 years 26 days ago
2003
Springer
As compared to a complex single processor based system, on-chip multiprocessors are less complex, more power efficient, and easier to test and validate. In this work, we focus on a...
HPCA
1998
IEEE
13 years 12 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
FCCM
1999
IEEE
13 years 12 months ago
1999
IEEE
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
PDP
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
TPDS
1998
13 years 7 months ago
1998
—The way the processes in a parallel program are scheduled on the processors of a multiprocessor system affects the performance significantly. Finding a schedule of processes to ...