453 search results - page 55 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
IFIP
1998
Springer
14 years 1 months ago
1998
Springer
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
FCCM
2009
IEEE
14 years 22 days ago
2009
IEEE
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
CASES
2008
ACM
13 years 11 months ago
2008
ACM
In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function ...
EGH
2010
Springer
13 years 6 months ago
2010
Springer
This paper proposes a massively parallel hardware architecture for efficient tracing of incoherent rays, e.g. for global illumination. The general approach is centered around hier...