453 search results - page 71 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
CJ
2004
13 years 8 months ago
2004
This paper describes a way to manage the modeling and analysis of Scheduled Maintenance Systems (SMS) within an analytically tractable context. We chose a significant case study h...
ICPP
2008
IEEE
14 years 3 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
HPCA
2005
IEEE
14 years 9 months ago
2005
IEEE
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
SC
2009
ACM
14 years 3 months ago
2009
ACM
Scientific workflow tools allow users to specify complex computational experiments and provide a good framework for robust science and engineering. Workflows consist of pipelines ...
EUROPAR
2007
Springer
14 years 3 months ago
2007
Springer
Abstract. Hardware Transactional Memory (HTM) gives software developers the opportunity to write parallel programs more easily compared to any previous programming method, and yiel...