453 search results - page 74 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
CGO
2003
IEEE
14 years 2 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
EUROSYS
2010
ACM
14 years 5 months ago
2010
ACM
Symmetric-ISA (instruction set architecture) asymmetricperformance multicore processors were shown to deliver higher performance per watt and area for codes with diverse architect...
VLDB
1999
ACM
14 years 1 months ago
1999
ACM
Recent high-performance processors employ sophisticated techniques to overlap and simultaneously execute multiple computation and memory operations. Intuitively, these techniques ...
ASPLOS
2004
ACM
14 years 2 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
ISPASS
2005
IEEE
14 years 2 months ago
2005
IEEE
A wide spectrum of e-commerce (B2B/B2C), banking, financial trading and other business applications require the exchange of data to be highly secure. The Secure Sockets Layer (SSL...