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» Execution levels for aspect-oriented programming
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ISCA
2007
IEEE
162views Hardware» more  ISCA 2007»
14 years 2 months ago
BulkSC: bulk enforcement of sequential consistency
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...
Luis Ceze, James Tuck, Pablo Montesinos, Josep Tor...
ASAP
2005
IEEE
133views Hardware» more  ASAP 2005»
14 years 1 months ago
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
IPPS
2005
IEEE
14 years 1 months ago
User Transparent Parallel Processing of the 2004 NIST TRECVID Data Set
The Parallel-Horus framework, developed at the University of Amsterdam, is a unique software architecture that allows non-expert parallel programmers to develop fully sequential m...
Frank J. Seinstra, Cees Snoek, Dennis Koelma, Jan-...
EMSOFT
2005
Springer
14 years 1 months ago
Using de-optimization to re-optimize code
The nature of embedded systems development places a great deal of importance on meeting strict requirements in areas such as static code size, power consumption, and execution tim...
Stephen Hines, Prasad Kulkarni, David B. Whalley, ...
ICCS
2005
Springer
14 years 1 months ago
Performance and Scalability Analysis of Cray X1 Vectorization and Multistreaming Optimization
Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hard...
Sadaf R. Alam, Jeffrey S. Vetter