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121
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IPPS
2007
IEEE
15 years 8 months ago
VoroNet: A scalable object network based on Voronoi tessellations
In this paper, we propose the design of VoroNet, an objectbased peer to peer overlay network relying on Voronoi tessellations, along with its theoretical analysis and experimental...
Olivier Beaumont, Anne-Marie Kermarrec, Loris Marc...
ISCAS
2005
IEEE
146views Hardware» more  ISCAS 2005»
15 years 8 months ago
A novel approach for network on chip emulation
— Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon...
Nicolas Genko, David Atienza, Giovanni De Micheli,...
FSS
2010
147views more  FSS 2010»
15 years 1 months ago
A divide and conquer method for learning large Fuzzy Cognitive Maps
Fuzzy Cognitive Maps (FCMs) are a convenient tool for modeling and simulating dynamic systems. FCMs were applied in a large number of diverse areas and have already gained momentu...
Wojciech Stach, Lukasz A. Kurgan, Witold Pedrycz
137
Voted
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 8 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
ASYNC
2003
IEEE
86views Hardware» more  ASYNC 2003»
15 years 7 months ago
A High-Speed Clockless Serial Link Transceiver
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
John Teifel, Rajit Manohar