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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
INFOCOM
1999
IEEE
14 years 13 hour ago
A Model for Window Based Flow Control in Packet-Switched Networks
Recently, networks have increased rapidly both in scale and speed. Problems related to the control and management are of increasing interest. The average throughput and end-to-end ...
Xiaowei Yang
SIGMETRICS
2002
ACM
117views Hardware» more  SIGMETRICS 2002»
13 years 7 months ago
Context-aware TCP/IP
Abstract-This paper discusses the design and evaluation of CATNIP, a ContextAware Transport/Network Internet Protocol for the Web. This integrated protocol uses application-layer k...
Carey L. Williamson, Qian Wu
ICC
2009
IEEE
14 years 2 months ago
HELP: // Hypertext In-Emergency Leveraging Protocol
—This paper proposes HELP://, a simple light-weight protocol that runs over HTTP and is used to disseminate information from a server(s) to its clients during the time of a crisi...
Mina Guirguis, Hideo Goto
ICCAD
2007
IEEE
139views Hardware» more  ICCAD 2007»
14 years 2 months ago
Using functional independence conditions to optimize the performance of latency-insensitive systems
—In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamic...
Cheng-Hong Li, Luca P. Carloni