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» Experiences with Parallel N-Body Simulation
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ICS
2007
Tsinghua U.
14 years 1 months ago
An L2-miss-driven early register deallocation for SMT processors
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
Joseph J. Sharkey, Dmitry V. Ponomarev
MIDDLEWARE
2004
Springer
14 years 21 days ago
Architecture for resource allocation services supporting interactive remote desktop sessions in utility grids
Emerging large scale utility computing systems like Grids promise computing and storage to be provided to end users as a utility. System management services deployed in the middle...
Vanish Talwar, Bikash Agarwalla, Sujoy Basu, Raj K...
ICCS
2001
Springer
13 years 11 months ago
High-Performance Algorithm Engineering for Computational Phylogenetics
Abstract. Phylogeny reconstruction from molecular data poses complex optimization problems: almost all optimization models are NP-hard and thus computationally intractable. Yet app...
Bernard M. E. Moret, David A. Bader, Tandy Warnow
TSP
2010
13 years 2 months ago
Distributed sparse linear regression
The Lasso is a popular technique for joint estimation and continuous variable selection, especially well-suited for sparse and possibly under-determined linear regression problems....
Gonzalo Mateos, Juan Andrés Bazerque, Georg...
GLVLSI
2011
IEEE
344views VLSI» more  GLVLSI 2011»
12 years 11 months ago
Circuit design of a dual-versioning L1 data cache for optimistic concurrency
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
Azam Seyedi, Adrià Armejach, Adrián ...