Sciweavers

192 search results - page 23 / 39
» Experiences with the Blackfin architecture in an embedded sy...
Sort
View
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 8 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
ISORC
2009
IEEE
14 years 2 months ago
Thread-Local Scope Caching for Real-time Java
There is increasing convergence between the fields of parallel and embedded computing. The demand for more functionality in embedded devices means that complex multicore architec...
Andy J. Wellings, Martin Schoeberl
ISBI
2006
IEEE
14 years 8 months ago
Development of a research interface for image guided intervention: initial application to epilepsy neurosurgery
This paper describes the development and application of methods to integrate research image analysis methods and software with a commercial image guided surgery navigation system ...
Xenophon Papademetris, Kenneth P. Vives, Marcello ...
RTAS
1997
IEEE
13 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
EWSA
2005
Springer
14 years 1 months ago
On the Systematic Conformance Check of Software Artefacts
Abstract. In this paper we present a systematic check of the conformance of the implemented and the intended software architecture. Nowadays industry is confronted with rapidly evo...
Hylke W. van Dijk, Bas Graaf, Rob Boerman