VLSID 2001 - PDF Preprint Papers

VLSID 2001 International Conference on VLSI Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed VLSID-2001 Paper

click to vote

VLSID
2001
IEEE

200views VLSI» more VLSID 2001»

Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures

14 years 11 months ago

Download esdat.ucsd.edu

The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...

Kanishka Lahiri, Sujit Dey, Anand Raghunathan

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	200	Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures	claim
2	184	Battery Life Estimation of Mobile Embedded Systems	claim
3	179	Low-Power Wireless Sensor Networks	claim
4	169	Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits	claim
5	164	An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers	claim
6	144	Next Generation Network Processors	claim
7	132	Accurate Power Macro-modeling Techniques for Complex RTL Circuits	claim
8	129	Design Of Provably Correct Storage Arrays	claim
9	129	Power-aware Multimedia Systems using Run-time Prediction	claim
10	118	Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language	claim
11	117	Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces	claim
12	104	Partitioning Routing Area into Zones with Distinct Pins	claim
13	98	Complexity Of Minimum-Delay Gate Resizing	claim
14	93	A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers	claim
15	88	Switching Noise Analysis Framework For High Speed Logic Families	claim
16	82	High Level Synthesis Of Multi-Precision Data Flow Graphs	claim
17	82	Efficient Signature-Based Fault Diagnosis Using Variable Size Windows	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers