This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
STGs give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondet...
The events of a security protocol and their causal dependency can play an important role in the analysis of security properties. This insight underlies both strand spaces and the ...
We describe an approach to using one logic to reason about specifications written in a second logic. One level of logic, called the "reasoning logic", is used to state th...
Today’s cross-organizations are increasingly coordinating their capabilities in the quest of dynamically adaptable and thus highly competitive realistic services. Unfortunately,...