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EH
2004
IEEE
115views Hardware» more  EH 2004»
14 years 2 months ago
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Progr...
Jörg Langeheine, Karlheinz Meier, Johannes Sc...
CLEF
2006
Springer
14 years 2 months ago
Overview of the CLEF 2006 Multilingual Question Answering Track
Having being proposed for the fourth time, the QA at CLEF track has confirmed a still raising interest from the research community, recording a constant increase both in the numbe...
Bernardo Magnini, Danilo Giampiccolo, Pamela Forne...
FPGA
2004
ACM
128views FPGA» more  FPGA 2004»
14 years 2 months ago
Incremental physical resynthesis for timing optimization
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
DAC
2006
ACM
14 years 2 months ago
Refined statistical static timing analysis through
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
DAGM
2006
Springer
14 years 2 months ago
Linear vs. Nonlinear Feature Combination for Saliency Computation: A Comparison with Human Vision
In the heart of the computer model of visual attention, an interest or saliency map is derived from an input image in a process that encompasses several data combination steps. Whi...
Nabil Ouerhani, Alexandre Bur, Heinz Hügli