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» Explaining Dynamic Cache Partitioning Speed Ups
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PADS
2003
ACM
14 years 29 days ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
PRL
2002
70views more  PRL 2002»
13 years 7 months ago
On the use of nearest feature line for speaker identification
As a new pattern classification method, nearest feature line (NFL) provides an effective way to tackle the sort of pattern recognition problems where only limited data are availab...
Ke Chen 0001, Ting-Yao Wu, HongJiang Zhang
PDCN
2004
13 years 9 months ago
Speculative prefetching of optional locks in distributed systems
We present a family of methods for speeding up distributed locks by exploiting the uneven distribution of both temporal and spatial locality of access behaviour of many applicatio...
Thomas Schöbel-Theuer
MICRO
2006
IEEE
94views Hardware» more  MICRO 2006»
13 years 7 months ago
A Sampling Method Focusing on Practicality
In the past few years, several research works have demonstrated that sampling can drastically speed up architecture simulation, and several of these sampling techniques are already...
Daniel Gracia Pérez, Hugues Berry, Olivier ...
OOPSLA
2004
Springer
14 years 1 months ago
The garbage collection advantage: improving program locality
As improvements in processor speed continue to outpace improvements in cache and memory speed, poor locality increasingly degrades performance. Because copying garbage collectors ...
Xianglong Huang, Stephen M. Blackburn, Kathryn S. ...