504 search results - page 12 / 101 » Explaining Verification Conditions |
ETFA
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new approach to modelling and verification of function block applications of the IEC 61499 standard. The approach uses the language of logic programming Prol...
FORTE
2009
13 years 5 months ago
2009
Abstract. We propose a verification method for parameterized systems with global conditions. The method is based on context-sensitive constraints, a symbolic representation of infi...
SCHOLARPEDIA
2008
13 years 7 months ago
2008
: We describe computer simulation of a number of associative models of classical conditioning in an attempt to assess the strengths and weaknesses of each model. The behavior of th...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
FOSSACS
2009
Springer
13 years 11 months ago
2009
Springer
In quantitative verification, system states/transitions have associated costs, and these are used to associate mean-payoff costs with infinite behaviors. In this paper, we propose ...