375 search results - page 19 / 75 » Explicit gate delay model for timing evaluation |
CVPR
2011
IEEE
13 years 3 months ago
2011
IEEE
Scene understanding from a monocular, moving camera is a challenging problem with a number of applications including robotics and automotive safety. While recent systems have show...
CPE
2000
Springer
14 years 9 hour ago
2000
Springer
Abstract. This paper presents TimeNET, a software tool for the modelling and performability evaluation using stochastic Petri nets. The tool has been designed especially for models...
MEMOCODE
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
ATS
2000
IEEE
14 years 2 days ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
Electrical Modeling for High Bandwidth IO Link Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR Prateek Bhansali ¬ Univ. of Minnesota, Mi...