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BMCBI
2008
214views more  BMCBI 2008»
13 years 7 months ago
Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
Yoginder S. Dandass, Shane C. Burgess, Mark Lawren...
ICPP
2009
IEEE
14 years 2 months ago
Exploiting Simulation Slack to Improve Parallel Simulation Speed
Parallel simulation is a technique to accelerate microarchitecture simulation of CMPs by exploiting the inherent parallelism of CMPs. In this paper, we explore the simulation para...
Jianwei Chen, Murali Annavaram, Michel Dubois
BMCBI
2010
109views more  BMCBI 2010»
13 years 7 months ago
FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. Th...
Stephanie Zierke, Jason D. Bakos
ANCS
2010
ACM
13 years 5 months ago
The case for hardware transactional memory in software packet processing
Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and acceler...
Martin Labrecque, J. Gregory Steffan
FCCM
1998
IEEE
89views VLSI» more  FCCM 1998»
13 years 12 months ago
A Run-Time Reconfigurable Engine for Image Interpolation
Custom Computing Machines (CCM's) have demonstrated significant performance advantages over general-purpose processors for certain classes of problems. However, problems can ...
Rhett D. Hudson, David I. Lehn, Peter M. Athanas