Sciweavers

87 search results - page 13 / 18
» Exploiting Instruction Redundancy for Transient Fault Tolera...
Sort
View
IPPS
2006
IEEE
14 years 1 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
DAC
2005
ACM
14 years 8 months ago
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome,...
ETS
2006
IEEE
122views Hardware» more  ETS 2006»
13 years 11 months ago
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics
Online repair through reconfiguration is a particularly advantageous approach in the nanoelectronic environment since reconfigurability is naturally supported by the devices. Howe...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
HPCA
2008
IEEE
14 years 7 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
11 years 10 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...