87 search results - page 8 / 18 » Exploiting Instruction Redundancy for Transient Fault Tolera... |
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
TVLSI
2002
13 years 7 months ago
2002
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
DSN
2008
IEEE
13 years 9 months ago
2008
IEEE
CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Wherea...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
ASPLOS
2000
ACM
13 years 12 months ago
2000
ACM
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...