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CODES
2010
IEEE
13 years 5 months ago
Automatic parallelization of embedded software using hierarchical task graphs and integer linear programming
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
Daniel Cordes, Peter Marwedel, Arindam Mallik
IEEEPACT
2000
IEEE
14 years 3 days ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 2 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
PAAMS
2010
Springer
13 years 6 months ago
A GPU-Based Multi-agent System for Real-Time Simulations
The huge number of cores existing in current Graphics Processor Units (GPUs) provides these devices with computing capabilities that can be exploited by distributed applications. I...
Guillermo Vigueras, Juan M. Orduña, Miguel ...
CGF
2010
105views more  CGF 2010»
13 years 7 months ago
Streaming-Enabled Parallel Dataflow Architecture for Multicore Systems
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
Huy T. Vo, Daniel K. Osmari, Brian Summa, Jo&atild...