87 search results - page 15 / 18 » Exploiting Postdominance for Speculative Parallelization |
ISCAPDCS
2003
13 years 11 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
HIPEAC
2009
Springer
14 years 4 months ago
2009
Springer
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
APCSAC
2003
IEEE
14 years 1 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
ISBI
2007
IEEE
14 years 4 months ago
2007
IEEE
Emerging multi-core processors are able to accelerate medical imaging applications by exploiting the parallelism available in their algorithms. We have implemented a mutual-inform...
ICVS
2001
Springer
14 years 2 months ago
2001
Springer
Abstract. At the first ICVS, we presented SA-C (“sassy”), a singleassignment variant of the C programming language designed to exploit both coarse-grain and fine-grain parallel...